A printed circuit board (PCB) includes a number of signal traces on a number of different layers that can be interconnected to form an interconnect topology. The interconnection of signal traces between the layers is often made using metal deposited through vias in the PCB that connects the two signal traces together. The portion of a via that extends through the PCB beyond the portion that interconnects the layers to form a signal path is referred to as a via stub.
A long via stub on PCB platforms is usually capacitive in nature and causes large return loss and undesirable resonance behavior. A long via stub has been known to cause problems for high-speed serial input/output (IO) platform signaling, especially for server 10+ layer backplane topologies, and for beyond 10 Gbps data rate (e.g., 10GBASE KR, 11G Quick Path Interconnect (QPI), 16G PCI-Express Gen 4 (PCIe4), 25-40G Serializer/Deserializer (SerDes). While compensation for PCB conductor and dielectric loss can be made with equalization circuits and PCB crosstalk can be addressed with stripline interconnections, reflections due to via stubs are hard to compensate for or cancel out, even using a limited tap decision feedback equalizer (DFE). This phenomenon becomes more prominent if lower loss PCB materials are used and the data rate goes higher, in which case long via stubs can completely impair a link without proper mitigation.
The worst case via stub occurs when signal transits from a layer 1 microstrip to a layer 3 stripline, i.e., when a via is used to connect a trace on layer 1 to a trace on layer 3. The worst case stub length can be as long as 90 to 120 mils (or even longer), depending on the board thickness. Due to layout space constraints and discrete components (e.g., alternating current (AC) coupling capacitor, electromagnetic interference (EMI) filter, on-board electro static discharge (ESD), a worst case via stub is almost unavoidable when routing multiple layer PCBs.
Long stubs associated with the press-fit connectors are even more problematic. For a high-speed serial interface like PCI-Express Gen 2 (PCIe2), the number of via stubs could be 10 or more, when considering that there are two via stubs for AC coupling capacitors, two via stubs for logic analyzers, two via stubs for each connector, and one via stub for each silicon package. Therefore, via stubs are one of the key challenges when designing platform interconnect solutions for PCIe2.
Some of the most effective mitigations on the via stub effect are via back drilling (to remove via stubs that are not in the interconnection path) or micro-vias (where unnecessary stubs are not in the design in the first place, requiring High Density Interconnects (HDI) board technology. However, they are generally too costly to implement from a manufacturing perspective even for server platforms. An alternative approach to the problems associated with via stub effects is through inductive compensation with special routing of the PCB traces close to the via stub, to increase the inductance and cancel out via the stub capacitance. This approach has frequency limitations and implications on PCB real estate. A third approach is to add more DFE taps or introduce new DFE architectures (e.g., floating tap DFE) that are more effective in mitigating reflections. This involves higher design complexity and risk and usually requires higher input/output (IO) power consumption and larger die size.
Traditionally, the differential positive and differential negative vias are routed in a perfectly symmetric fashion to optimize for differential signal transmission. In other words, the vias used to connect signal traces of different layers in a PCB are aligned with each other and any ground stitching vias.